1. Field of the Invention
The present invention relates generally to digital correlation devices, but more particularly to a digital m of n correlation device encompassing a fast correlation product for pulse compression modulations such as phase or frequency shift keying, where m is equal to the number of agreements of signal and reference bits, and n is equal to the total number of bits.
2. Description of the Prior Art
In the field of radar the conflicting requirements of a short pulse for range resolution and a long pulse for increased probability of target detection have led to the development of radar pulse compression techniques for satisfying both of the foregoing requirements simultaneously. Pulse compression is accomplished by modulation of the carrier wave. For a given probability of detection with a peak power limited radar, the pulse duration will be determined by the peak and average power limitations. The precision of the range resolution will then be established by the number of bits in the overall pulse. The bandwidth time product .beta.T is a measure of the compression gained and is always greater that one (1) for pulse compression. Increasing the range resolution requires that the speed at which compression is accomplished be increased. The correlation device disclosed herein produces a very fast correlation product for pulse compression modulations such as phase or frequency shift keying. The compression ratio for the correlation device according to the present invention is 168:1 (equal to the number of bits). Moreover, the correlation bit rate is in excess of 100 Mbps, a speed heretofore unattained in the prior art. The correlation device is also well suited for large scale integration (LSI) fabrication. Hence, based on the foregoing it appears that a correlation device incorporating the concepts of the present invention is needed in the prior art.
In the past, both analog and digital summation processes and circuits for digital correlation have been used. The prevalent practice in the prior art is to add modulo 2 the bits in corresponding bit positions in reference and signal shift registers. This output, indicating the number of agreements by a binary ONE (or ZERO) in each bit position for which there is an agreement, is then summed either digitally or by analog techniques.
In the digital summation approach, the modulo 2 outputs are presented to an n-bit adder tree that converts the number of simultaneous ONE's presented on the n lines into a binary number. This binary number is then compared digitally with a desired threshold. The basic problem with the adder tree approach is that, as n increases, the size thereof becomes disproportionately large. Consequently, there is a need in the prior art to increase n without a disproportionate increase in size of the digital correlation device.
In the analog summation approach, the modulo 2 outputs are used to drive 1-bit digital-to analog (D/A) converters. The individual outputs from the D/A converters are summed to provide an analog representation of the total number of agreements. This value is then compared to an analog threshold in an analog comparator. The basic problem with the analog approach is the limitation on the speed that can be obtained when a large number of the 1-bit D/A converter outputs are brought together for analog summation. The capacitance created at the resulting node is the limiting factor on speed. Hence there is a need in the prior art to be able to use the analog summation approach but yet not limit the speed of correlation.
An example of the use of analog summation is disclosed in U.S. Pat. No. 3,670,151 to Lindsay et al, entitled "Correlators Using Shift Registers", filed June 5, 1970, and assigned to the same assignee as the present invention. Lindsay et al disclose, inter alia, a block diagram representation of a correlator using two shift registers having multivibrators whose outputs are summed by modulo 2 adders. The outputs of the adders are summed through a plurality of resistors functioning as 1-bit D/A converters. While Lindsay et al disclose basic concepts similar to the present invention, i.e., the use of signal and reference shift registers, modulo 2 addition and analog summation, the elements and techniques used are different from those used in the present invention and are not as conducive to high speed operation as the present invention.
Additional prior art such as U.S. Pat. No. 3,831,013 to Alsup et al, entitled, "Correlators Using Shift Registers" filed Feb. 20, 1973, and U.S. Pat. No. 3,303,335 to Pryor, entitled, "Digital Correlation System Having An Adjustable Impulse Generator", filed Apr. 25, 1963, and assigned to the same assignee as the present invention, and the prior art, as indicated hereinabove, include advances in digital correlation devices, including improvements in the signal to noise ratio, the adaptability for implementation by integrated circuitry and the use of shift registers as primary elements. However, insofar as can be determined, no prior art digital correlation device incorporates all of the improvements, features and advantages of the present invention.